1. Field of the Invention
This invention relates to the field of electronic circuit design and, more particularly, to timing analysis for circuit designs implemented with integrated circuits.
2. Description of the Related Art
A programmable logic device (PLD) is a type of integrated circuit (IC), that can be programmed to perform specified logic functions. Other types of ICs can include application specific integrated circuits (ASICs) and application specific standard products (ASSPs). Modern PLDs, for example, are large, complex devices that can be programmed to perform a range of different functions. Conventional circuit design techniques traditionally task one designer, or design team, with developing a circuit design for a given IC. As ICs have become more complex, however, so too have the circuit designs intended to be used with such devices.
In consequence, a technique referred to as modular design has been gaining in popularity. Modular design seeks to reduce or minimize the complexity of circuit design. Modular design refers to the subdivision of a circuit design into several different modules, or sub-circuits. Each module can be assigned to one or more designers, or teams of designers, as the case may be. This technique allows each team to direct its efforts to one aspect of the design, i.e. its assigned module. Subsequently, the modules developed by each design team can be brought together and combined to form the completed circuit design.
In light of the popularity of modular design, some design tools have begun offering modular design functions. These tools, however, suffer from several limitations, particularly relating to timing analysis. One such limitation relates to local timing analysis. Conventional design tools tend to be inaccurate when performing module level timing analysis. Such is the case as conventional design tools do not provide a means of apportioning global timing constraints for a circuit design to individual modules. In other words, while timing constraints can be applied on a global level, conventional design tools are unable to accurately determine which portions of global design constraints are attributable to a given module. Without the ability to accurately translate global timing constraints to local timing constraints, it becomes unlikely that global timing constraints will be met when individual modules are combined.
Another limitation of conventional design tools relates to global timing analysis. Specifically, performing global timing analysis often is costly in terms of time and computing resources. When performing timing analysis for an entire circuit design, conventional design tools consider the complete implementation details for each module of the design. This means that the netlist for the entire circuit design, or the netlist for each module of the design, must be considered. Netlists, however, tend to be large in size, requiring significant memory to store and process. The netlists must be loaded into memory and processed to compute path delays which then can be compared with the global timing constraints. In some cases, this process can take hours to complete.
It would be beneficial to have a design methodology which facilitates modular design for ICs in a manner that overcomes the deficiencies described above.